MMCM Ports

CLKIN1

Input

General clock input. See CLKIN1 – Primary Reference Clock Input .

CLKIN2

Input

Secondary clock input for the MMCM reference clock. See CLKIN2 – Secondary Clock Input .

CLKFBIN

Input

Feedback clock input. See CLKFBIN – Feedback Clock Input .

CLKINSEL

Input

This signal controls the state of the clock input MUX, High = CLKIN1, Low = CLKIN2. CLKINSEL dynamically switches the MMCM reference clock. See CLKINSEL – Clock Input Select .

RST

Input

Asynchronous reset signal. The RST signal is an asynchronous reset for the MMCM. The MMCM synchronously re-enables itself when this signal is released (i.e., MMCM re-enabled). A reset is required when the input clock conditions change (e.g., frequency). See RST – Asynchronous Reset Signal .

PWRDWN

Input

Powers down instantiated but unused MMCMs. See PWRDWN – Power Down .

DADDR[6:0]

Input

The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. See DADDR[6:0] – Dynamic Reconfiguration Address .

DI[15:0]

Input

The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. See DI[15:0] – Dynamic Reconfiguration Data Input .

DWE

Input

The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low. See DWE – Dynamic Reconfiguration Write Enable .

DEN

Input

The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. See DEN – Dynamic Reconfiguration Enable Strobe .

DCLK

Input

The DCLK signal is the reference clock for the dynamic reconfiguration port. See DCLK – Dynamic Reconfiguration Reference Clock .

PSCLK

Input

Phase shift clock. See PSCLK – Phase Shift Clock .

PSEN

Input

Phase shift enable. See PSEN – Phase Shift Enable .

PSINCDEC

Input

Phase shift increment/decrement control. See PSINCDEC – Phase Shift Increment/Decrement Control .

CLKOUT[0:6]

Output

User configurable clock outputs (0 through 6) that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.

CLKOUT[0:3]B

Output

Inverted CLKOUT[0:3]. See CLKOUT[0:3]B – Inverted Output Clocks .

CLKFBOUT

Output

Dedicated MMCM feedback output. See CLKFBOUT – Dedicated MMCM Feedback Output .

CLKFBOUTB

Output

Inverted CLKFBOUT. See CLKFBOUTB – Inverted CLKFBOUT .

CLKINSTOPPED

Output

Status pin indicating that the input clock has stopped. See CLKINSTOPPED – Input Clock Status .

CLKFBSTOPPED

Output

Status pin indicating that the feedback clock has stopped. See CLKFBSTOPPED – Feedback Clock Status .

LOCKED

Output

An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (e.g., input clock phase shift). The MMCM must be reset after LOCKED is deasserted.

DO[15:0]

Output

The dynamic reconfiguration output bus provides MMCM data output when using dynamic reconfiguration. See DO[15:0] – Dynamic Reconfiguration Output Bus .

DRDY

Output

The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the MMCM’s dynamic reconfiguration feature. See DRDY – Dynamic Reconfiguration Ready .

PSDONE

Output

Phase shift done. See PSDONE – Phase Shift Done .

CDDCREQ

Input

Requests a dynamic frequency change for selected clock outputs. See MMCM Clock Divide Dynamic Change .

CDDCDONE

Output

Signals that the dynamic frequency change is completed. See MMCM Clock Divide Dynamic Change .

Notes:

1. All control and status signals except PSINCDEC are active High.