The MMCME#_ADV primitive provides access to all MMCME#_BASE features plus additional ports for clock switching, access to the dynamic reconfiguration port (DRP), and dynamic fine-phase shifting. The MMCME#_ADV ports are listed in Table: MMCME#_ADV Ports .
The MMCM is a mixed-signal block designed to support clock network deskew, frequency synthesis, and jitter reduction. These three modes of operation are discussed in more detail in this section. The VCO operating frequency can be determined by using the following relationship:
Equation 3-1
Equation 3-2
where the M, D, and O counters are shown in This Figure . The value of M corresponds to the CLKFBOUT_MULT_F setting, the value of D to the DIVCLK_DIVIDE, and O to the CLKOUT_DIVIDE.
The seven “O” counters can be independently programmed. For example, O0 can be programmed to do a divide-by-two while O1 is programmed for a divide-by-three. The only constraint is that the VCO operating frequency must be the same for all the output counters because a single VCO drives all the counters.