In UltraScale ™ architecture-based devices, the clock management tile (CMT) includes a mixed-mode clock manager (MMCM) and two phase-locked loops (PLLs). The main purpose of the PLL is to generate clocking for the I/Os. But it also contains a limited subset of the MMCM functions that can be used for general clocking purposes.
The clock input connectivity allows multiple resources to provide the reference clock(s) to the MMCM. The number of output counters (dividers) is eight, with some of them capable of driving out an inverted clock signal (180° phase shift). MMCMs have infinite fine phase shift capability in either direction and can be used in dynamic phase shift mode. The resolution of the fine phase shift depends on the voltage-controlled oscillator (VCO) frequency. Fractional divide functionality in increments of 1/8th (0.125) for CLKFBOUT and CLKOUT0 are available to support greater clock frequency synthesis capability. UltraScale architecture-based devices have a spread spectrum (SS) capability. If the MMCM spread-spectrum feature is not used, a spread spectrum on an external input clock will not be filtered and thus passed on to the output clock.