Table: PLL Ports summarizes the PLL ports.
|
Pin Name |
I/O |
Pin Description |
|---|---|---|
|
CLKIN |
Input |
General clock input. |
|
RST |
Input |
Asynchronous reset signal. The RST signal is an asynchronous reset for the PLL. The PLL synchronously re-enables itself when this signal is released (i.e., PLL re-enabled). A reset is required when the input clock conditions change (e.g., frequency). |
|
PWRDWN |
Input |
Powers down instantiated but unused PLLs. See PWRDWN – Power Down . |
|
CLKOUT[0:1] CLKOUT[0:1]B |
Output |
User configurable clock outputs 0 and 1 and their inverted versions. The CLKOUT can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. |
|
CLKFBOUT |
Output |
Dedicated PLLE3 or PLLE4 feedback output. |
|
CLKFBIN |
Input |
Feedback clock input. |
|
CLKOUTPHYEN |
Input |
Enable PHY clocking. |
|
CLKOUTPHY |
Output |
Dedicated PHY clock. |
|
LOCKED |
Output |
An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on; no extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (e.g., input clock phase shift). The PLL must be reset after LOCKED is deasserted. |
|
DADDR[6:0] |
Input |
The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros. |
|
DI[15:0] |
Input |
The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero. |
|
DWE |
Input |
The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, DWE must be tied Low. |
|
DEN |
Input |
The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low. |
|
DCLK |
Input |
The DCLK signal is the reference clock for the dynamic reconfiguration port. |
|
DO[15:0] |
Output |
The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration. |
|
DRDY |
Output |
The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLL’s dynamic reconfiguration feature. |