Static Phase Shift Mode (MMCM and PLL)

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

The static phase shift (SPS) resolution in time units is defined as:

Equation 3-3 ug572_c3_Clock_Management00029.jpg

Because the VCO can provide eight phase-shifted clocks at 45° each; always providing possible settings for 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° of phase shift. The higher the VCO frequency is, the smaller the phase shift resolution. Because the VCO has a distinct operating range, it is possible to bound the phase shift resolution using from

ug572_c3_Clock_Management00031.jpg period.

Each CLKOUT output counter is individually programmable allowing each to have an additional phase shift resolution in degrees based on the phase of the VCO selected and the CLKOUT counter divide value. The granularity of the CLKOUT phase shift value can be calculated as 45°/CLKOUT_DIVIDE value. The maximum phase shift range is also determined by the CLKOUT_DIVIDE value. The maximum phase shift is 360° when CLKOUT_DIVIDE £ 64. When CLKOUT_DIVIDE is > 64, the maximum phase shift is:

Equation 3-4 ug572_c3_Clock_Management00033.jpg

It is possible to phase shift the CLKFBOUT feedback clock. In that case, all CLKOUT output clocks are negatively phase shifted with respect to CLKIN.

The two fractional counters (CLKFBOUT and CLKOUT0) also have static phase shift capability. A phase shift step is defined as:

Equation 3-5 ug572_c3_Clock_Management00035.jpg

For example, if the fractional divide value is 2.125, a static phase shift step is 360/(2.125 x 8) = 21.176 degrees.