Zero Delay Buffer

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

The MMCM can also be used to generate a zero delay buffer clock. A zero delay buffer can be useful for applications where there is a single clock signal fanout to multiple destinations with a low skew between them. This configuration is shown in This Figure . Here, the feedback signal drives off chip and the board trace feedback is designed to match the trace to the external components. In this configuration, it is assumed that the clock edges are aligned at the input of the UltraScale device and the input of the external component. The input clock buffers for CLKIN and CLKFBIN must be in the same bank.

Figure 3-11: Zero Delay Buffer

X-Ref Target - Figure 3-11


In some cases, precise alignment cannot occur because of the difference in loading between the input capacitance of the external component and the feedback path capacitance of the UltraScale device . For example, the external components can have an input capacitance of 1 pF to 4 pF while the part has an input capacitance as specified in the UltraScale device data sheets [Ref 5] . There is a difference in the signal slope, which is basically skew. Designers should be aware of this effect to ensure timing.