UltraScale FPGA ESD handling requirements are based on JEDEC JEP155, available at www.jedec.org/standards-documents/docs/jep-155, as well as Industry Council ESD-CDM Target Levels, JEP157, available at www.esdindustrycouncil.org/ic/en.
UltraScale FPGA ESD handling requirements are based on JEDEC JEP155, available at www.jedec.org/standards-documents/docs/jep-155, as well as Industry Council ESD-CDM Target Levels, JEP157, available at www.esdindustrycouncil.org/ic/en.