Even if two devices are footprint compatible from a design and PCB standpoint, FPGA package flight times will be different across different devices, so they will need to be accounted for. Flight time information can be found within the AMD Vivado™ tools during the I/O planning stage or after synthesis. The ideal strategy to account for pin flight time differences is to deskew the printed circuit board when migrating to the new device. If this is not possible, AMD recommends laying out the printed circuit board with the final device in mind to maximize system performance for the long term. System performance might have to be derated when using the initial device. As a last option, choosing the midpoint of the range of flight times and routing the board based on that value can act as a compromise, though maximum system performance might not be achievable with this method. Pin flight time information can be obtained via the Package Pins tab within the Vivado tools, both in the I/O planning stage and after synthesis.