The AMD UltraScale architecture integrated IP core for Interlaken is a highly configurable integrated IP core that can support an overall bandwidth up to 150 Gb/s for protocol logic transmission. The core connects to serial transceivers at defined rates up to 12.5 Gb/s with GTH transceivers, and up to 25.78125 Gb/s with GTY transceivers. The block consists of a number of dedicated locations that are located at different points on different devices. There are specific rules for connecting these dedicated blocks to specific transceiver locations, which might impact migration to another device. Refer to UltraScale Architecture Integrated IP Core for Interlaken LogiCORE IP Product Guide (PG169) [Ref 16] for a more comprehensive guide regarding the proper generation and verification of Interlaken interfaces in UltraScale devices with special attention to the Transceiver Interface section.