For programmable logic (PL), VCCINT, VCCINT_IO, and VCCBRAM have voltage limits that can differ across the speed and temperature grades as shown in Table: MPSoC PL Voltage Matrix by Speed/Temperature Grade. For the processing system (PS), VCC_PSINTFP, VCC_PSINTPL, VCC_PSINTFP_DDR, and VPS_MGTRAVCC can have voltage limits that differ across the speed and temperature grades as shown in Table: MPSoC PS Voltage Matrix by Speed/Temperature Grade.
Table 8-1: MPSoC PL Voltage Matrix by Speed/Temperature Grade
|
Speed/
Temperature Grade
|
VCCINT (V)
|
VCCINT_IO (V)
|
VCCBRAM (V)
|
|
-1E
|
0.85
|
0.85
|
0.85
|
|
-2E
|
0.85
|
0.85
|
0.85
|
|
-2LE
|
0.72 or 0.85
|
0.85
|
0.85
|
|
-3E
|
0.90
|
0.90
|
0.90
|
|
-1I
|
0.85
|
0.85
|
0.85
|
|
-1LI
|
0.72 or 0.85
|
0.85
|
0.85
|
|
-2I
|
0.85
|
0.85
|
0.85
|
|
Notes:
1.VCCINT_IO must connect to VCCBRAM.
|
Table 8-2: MPSoC PS Voltage Matrix by Speed/Temperature Grade
|
Speed/Temperature Grade
|
VCC_PSINTFP (V)
|
VCC_PSINTLP (V)
|
VCC_PSINTFP_DDR (V)
|
VPS_MGTRAVCC(V)
|
|
-1E
|
0.85
|
0.85
|
0.85
|
0.85
|
|
-2LE
|
0.85
|
0.85
|
0.85
|
0.85
|
|
-3E
|
0.90
|
0.90
|
0.90
|
0.85
|
|
-1I
|
0.85
|
0.85
|
0.85
|
0.85
|
|
-1LI
|
0.85
|
0.85
|
0.85
|
0.85
|
|
-2I
|
0.85
|
0.85
|
0.85
|
0.85
|
|
Notes:
1.VCC_PSINTFP_DDR must connect to VCC_PSINTFP.
|