3. Power Supply Voltage Levels and VCCINT_IO Connection

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

For UltraScale and UltraScale+ FPGAs in the -3, -2, or -1 speed grades, it is required to connect VCCINT_IO to VCCINT and VCCBRAM. However, for UltraScale+ -2L and -1L FPGAs, it is required to connect VCCINT_IO to VCCBRAM.

To support this requirement, the system shown in Table: VCCINT/VCCINT_IO/VCCBRAM Connection Matrix is recommended in conjunction with This Figure. The VCCBRAM plane must be sized appropriately to support the additional load for VCCINT_IO when using -2L or -1L devices.

It is possible to connect VCCINT, VCCINT_IO, and VCCBRAM together when using -2 or -1 devices because the respective voltages are the same. It is also possible to connect VCCINT, VCCINT_IO, and VCCBRAM together when using -2L or -1L devices if VCCINT is always operated at 0.85V.

Table 7-3:      VCCINT/VCCINT_IO/VCCBRAM Connection Matrix

 

-3, -2, -1

-2L, -1L

VCCINT_IO connection

VCCINT/VCCBRAM

VCCBRAM

VCCINT sense line connection

Averaged with VCCINT_IO

Single connection to VCCINT

VCCBRAM sense line connection

Single connection to VCCBRAM

Averaged with VCCINT_IO

R1

0W 0603

0W 0603

R2

0W 0603

Do not populate

R3

10W 0603

10W 0603

R4

10W 0603

Do not populate

R5

Do not populate

10W 0603

R6

10W 0603

10W 0603

Figure 7-1:      Reference Layout to Support VCCINT/VCCINT_IO/VCCBRAM Connection Matrix

X-Ref Target - Figure 7-1

X18639-c7-01.jpg