HRIO banks in UltraScale FPGAs become HPIO banks in Virtex UltraScale+ FPGAs.
IMPORTANT: There are a number of cases in which two “half” banks in an UltraScale device correspond to one “full” bank in an UltraScale+ device, and vice versa. When migrating from a device with half banks to a device with full banks, ensure that the voltage level on all VCCO pins for the half banks match the intended voltage of the corresponding full bank. Refer to Table: Corresponding Half-Banks and Full-Banks and to the I/O bank migration table in UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) [Ref 9] to determine if this situation applies to your intended migration path.