•All GTH transceivers in UltraScale FPGAs become GTY transceivers in Virtex UltraScale+ FPGAs.
•Some GTY transceiver voltage levels change from UltraScale to UltraScale+ FPGAs, as noted in Table: Voltages Differences between UltraScale and UltraScale+ FPGAs.
•While still maintaining footprint compatibility, some devices might have one or more extra RCAL and RREF pins than smaller dies in the same package. If planning to migrate from a smaller die to a bigger die in the same package, AMD recommends reserving any extra RCAL and RREF pins for later use, because they are NC pins in the smaller devices.
•Special exceptions for the F1924 package are:
°VU11P-FLVF1924 GTY transceivers run up to 16.3 Gb/s versus the standard GTY transceiver speed of 32.75 Gb/s.
°Two ground pins (G9 and G10) in the UltraScale KU085/115 F1924 device later give way to becoming RREF (G9) and RCAL (G10) pins in the UltraScale+ VU11P F1924 device. The recommended way to design for this case would be by utilizing the schematic shown in This Figure and Table: Reserving RCAL and RREF Pins for F1924. When using the KU085/115 F1924, the G9 and G10 pins are grounded, and the resistors can be left unpopulated. When the RCAL and RREF pins are present when using the VU11P, both resistors should be populated.
