Some UltraScale devices are implemented with stacked silicon interconnect (SSI) technology, and certain implementations can only be contained within one SLR. SLRs are divided by a passive silicon interposer. Migrations that span multiple SLRs are not recommended. For example, DDR4 interfaces running at the maximum data rate must be contained within one SLR. See 8. Memory Interface Migration for a specific example of where the interposer can break an existing implementation.
The bank drawings in UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575) [Ref 9] identify SLRs connected by interposers.