7. Memory Interface PCB Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID: UG583
Release Date: 2023-11-14
Revision: 1.27 English

Table: DDR4 SDRAM Performance in UltraScale+ FPGAs in the Presence of Migration for Single-Rank Component illustrates the expected PL DDR4 SDRAM performance for UltraScale+ FPGAs in the presence of migration for a single-rank component.

Table 7-6: DDR4 SDRAM Performance in UltraScale+ FPGAs in the Presence of Migration for Single-Rank Component
DDR4 Data Rate in UltraScale FPGAs	V_CCINT = 0.9V	UltraScale+ V_CCINT = 0.85V		UltraScale+ V_CCINT = 0.72V
DDR4 Data Rate in UltraScale FPGAs	-3 (Max = 2667 Mb/s)	-2I, -2E, -2LE (Max = 2667 Mb/s)	-1E, -1I, (Max = 2400 Mb/s)	-2LE (Max = 2400 Mb/s)
-3 @ 2400	2400	2400	2133	2133
-3 @ 2133	2133	2133	2133	2133
-3 @ 1866	1866	1866	1866	1866
-2E, -2I @ 2400	2400	2400	2133	2133
-2E, -2I @ 2133	2133	2133	2133	2133
-2E, -2I @ 1866	1866	1866	1866	1866
-1, -1I @ 2133	2133	2133	2133	2133
-1, -1I @ 1866	1866	1866	1866	1866
Notes: 1.This table applies only to PL memory interfaces. PS interfaces do not derate in performance due to speed grade.