When migrating a memory interface from one device to another, it is important to verify that all pinout and banking restrictions remain valid. For example, most memory interfaces require the use of two or three consecutive banks in one column. In addition, memory interfaces in UltraScale devices should not cross SLR boundaries. Refer to UltraScale Architecture FPGAs Memory IP Product Guide (PG150) [Ref 13] for a more comprehensive guide regarding the proper generation and verification of UltraScale memory interfaces.