9. Integrated 100G Ethernet Migration

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

The 100G Ethernet IP core is a dedicated block that provides 100 Gb/s MAC and PCS logic capability. The block consists of a number of dedicated locations that are located at different points on different devices. There are specific rules for connecting these dedicated blocks to specific transceiver locations, which might impact migration to another device. In addition, the CAUI-4 and switchable CAUI-10/CAUI-4 modes require GTY transceivers.

Refer to UltraScale+ Devices Integrated 100G Ethernet Subsystem Product Guide (PG203) [Ref 28] for a more comprehensive guide regarding designing with the 100G Ethernet core, with special attention to the Transceiver Selection Rules section.