In always on, cost-optimized applications, where standard -1 or -2 speed grade devices are used, a significant amount of power rail consolidation is possible, assuming the decoupling and filtering requirements on the individual supplies as outlined in this document are met. Table: Always On: Cost-Optimized Power Rail Consolidation (-1 and -2 Devices) broadly defines the power rail consolidation that is possible for this use case. For further clarity, This Figure shows the possible power rail consolidation graphically.
As shown in Table: Always On: Cost-Optimized Power Rail Consolidation (-1 and -2 Devices), the minimum number of regulators required to power a Zynq UltraScale+ MPSoC in this use case is five. In many cases, five or more regulators can be provided by a single integrated power management integrated circuit (PMIC). For example power delivery solutions for AMD products, refer to Power Management Partners.
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|
Power Regulator |
Sequence |
Possible Power Rail Consolidation |
|---|---|---|---|
|
Required |
1 |
See Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22] |
VCCINT, VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_IO, VCCBRAM |
|
2 |
VCC_PSAUX, VCC_PSADC(1), VCC_PSDDR_PLL(2), VCCAUX, VCCAUX_IO, and VCCADC(1) |
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|
3 |
VCC_PSPLL, VMGTAVTT (GTH), and VMGTAVTT (GTY) |
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|
4 |
VCCO_PSDDR |
||
|
5 |
VCCO_PSIO[0:3] assuming all PS I/Os run from same voltage |
||
|
Required: |
9 |
VCCINT_VCU |
|
|
User-defined |
6 |
VPS_MGTRAVCC |
|
|
7 |
VPS_MGTRAVTT, VMGTVCCAUX (GTH), and VMGTVCCAUX (GTY) |
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|
8 |
VMGTAVCC (GTH) and VMGTAVCC (GTY) |
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|
10 |
Optional PL and PS I/O voltages |
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Notes: 1.Assuming rail is filtered as per UltraScale Architecture System Monitor User Guide (UG580) [Ref 25]. 2.Assuming rail is filtered as per VCC_PSDDR_PLL Supply. 3.When consolidating, ensure that all tolerances are met. |
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Note: In This Figure, the dashed lines are dependent on the user configuration. Identical voltages between I/O supplies and digital supplies can be combined if operating at the same voltage. This might alter the power sequence, moving the I/O supply up to the sequence slot of the rail it is combined with.
Depending on user configuration, more than five regulators might be required. Table: Number of Rails for “Always On: Optimized for Cost (-1 and -2 Devices)” Scenario details the number of regulators required to power Zynq UltraScale+ MPSoCs for a variety of device configurations. This Figure shows the power rail consolidation for the configuration requiring only five regulators using CG or EG devices.
Additional power regulators are typically required for termination voltages and reference voltages of the DDR memory associated to the PS or PL.
