Always On: Optimized for PL Performance (-3 Devices)

For the highest level of PL performance, AMD offers Zynq UltraScale+ MPSoCs in a -3 speed grade. For the -3 speed grade device, all the core rails (VCCINT, VCCINT_VCU, VCCBRAM, VCCINT_IO, VCC_PSINTLP, VCC_PSINTFP, and VCC_PSINTFP_DDR) are run at a nominal voltage of 0.9V.

Table: Always On: PL Performance-Optimized Rail Consolidation broadly defines the power rail consolidation that is possible for this use case, assuming the decoupling and filtering requirements on the individual supplies as outlined in this document are met. For further clarity, This Figure shows the possible power rail consolidation graphically. As shown in Table: Always On: PL Performance-Optimized Rail Consolidation, the minimum number of power regulators required to power a Zynq UltraScale+ MPSoC in this use case is five for non-EV devices, and six for EV devices.

Note:   In This Figure, the dashed lines are dependent on the user configuration. Identical voltages between I/O supplies and digital supplies can be combined if operating at the same voltage. This might alter the power sequence, moving the I/O supply up to the sequence slot of the rail it is combined with.

Table: Number of Power Regulators Required for “Always On: Optimized for PL Performance (-3 Devices)” Scenario shows the number of regulators for common configurations of Zynq UltraScale+ MPSoC used in this use case.