Always On: Optimized for Power and/or Efficiency (-1L and -2L Devices)

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

For applications requiring the lowest power dissipation and/or the highest efficiency, AMD offers the -1L and -2L speed grades. To achieve the highest efficiency and lowest power, the -1L and -2L devices can operate with a VCCINT voltage of 0.72V. To enable VCCINT to run at 0.72V an additional power regulator is required.

Other than the need for an additional power regulator for VCCINT, the possible power rail consolidation is similar to the previous use case. Table: Always On - Power/Efficiency Rail Consolidation for Low-Power Devices broadly defines what power rail consolidation is possible for this use case, assuming the decoupling and filtering requirements on the individual supplies as outlined in this document are met. For further clarity, This Figure shows the possible power rail consolidation graphically.

As shown in Table: Always On - Power/Efficiency Rail Consolidation for Low-Power Devices, the minimum number of regulators required for this use case is six.

Table 1-4:      Always On - Power/Efficiency Rail Consolidation for Low-Power Devices

 

Power Regulator

Sequence

Possible Power Rail Consolidation

Required

1

See Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 22]

VCCINT

2

VCC_PSINTFP, VCC_PSINTLP, VCC_PSINTFP_DDR, VCCINT_IO, and VCCBRAM

3

VCC_PSAUX, VCC_PSADC(1), VCC_PSDDR_PLL(2), VCCAUX, VCCAUX_IO and VCCADC(1)

4

VCC_PSPLL, VMGTAVTT (GTH), and VMGTAVTT (GTY)

5

VCCO_PSDDR

6

VCCO_PSIO[0:3] assuming all PS I/Os run from same voltage

Required - EV devices

10

VCCINT_VCU

User-defined

7

VPS_MGTRAVCC

8

VPS_MGTRAVTT, VMGTVCCAUX (GTH), and VMGTVCCAUX (GTY)

9

VMGTAVCC (GTH) and VMGTAVCC (GTY)

11

Optional PL and PS I/O voltages

Notes:

1.Assuming rail is filtered as per UltraScale Architecture System Monitor User Guide (UG580) [Ref 25].

2.Assuming rail is filtered as per VCC_PSDDR_PLL Supply.

Figure 1-6:      Always On: Power and/or Efficiency-Optimized Power Rail Consolidation for
Low-Power Devices

X-Ref Target - Figure 1-6

X18637-c4-23.jpg

Note:   In This Figure, the dashed lines are dependent on the user configuration. Identical voltages between I/O supplies and digital supplies can be combined if operating at the same voltage. This might alter the power sequence, moving the I/O supply up to the sequence slot of the rail it is combined with.

Table: Number of Power Regulators Needed for “Always On: Optimized for Power and/or Efficiency (-1L and -2L Devices)” Scenario shows the number of power regulators for a variety of common configurations of Zynq UltraScale+ MPSoC for this use case.

Table 1-5:      Number of Power Regulators Needed for “Always On: Optimized for Power and/or Efficiency (-1L and -2L Devices)” Scenario

Configuration

Number of Power Regulators

PS and PL DDR, 1.8V I/O and 2.5V or 3.3V I/O with no MGTs

Seven (1, 2, 3, 4, 5, 6, 10)

PS and PL DDR, 1.8V I/O, 2.5V I/O and 3.3V I/O with no MGTs

Eight (1, 2, 3, 4, 5, 6, 10, 11)

PS and PL DDR, 1.8V I/O, 2.5V or 3.3V I/O and PS MGTs

Nine (1, 2, 3, 4, 5, 6, 7, 8, 10)

PS DDR, 1.8V I/O, 3.3V I/O, PS MGTs and PL MGTs

Ten (1, 2, 3, 4, 5, 6, 7, 8, 9, 10)