Keeping the analog and clock signals as free as possible from any noise sources is essential, whether they be from the outside environment, or on the PCB itself. The following sections show various specifications and recommendations that result in optimal board and system performance.
To demonstrate the optimum data converter performance, AMD recommends that the PCB meet the signal integrity requirements set out in Table: Signal Integrity Specifications for DAC/ADC Pairs and Clocks. Refer to the sections below for more details regarding each type of specification.
|
Type |
Metric |
Maximum Frequency(1) |
|---|---|---|
|
RFDC Signaling |
Maximum Frequency |
4 GHz (Gen 1) 5 GHz (Gen 2) 6 GHz (Gen 3) 7 GHz (DFE) |
|
DIFF FEXT |
–70 dBc |
|
|
COMM FEXT |
–60 dBc |
|
|
DIFF NEXT |
–70 dBc |
|
|
COMM NEXT |
–60 dBc |
|
|
CMRR |
–38 dB |
|
|
DIFF RL |
–18 dB |
|
|
COMM RL |
–15 dB |
|
|
IL |
–2.0 dB |
|
|
RFDC Clocking |
Maximum Frequency |
6.4 GHz (Gen 1, Gen 2) 10 GHz (Gen 3) |
|
DIFF FEXT (DAC to ADC) |
–80 dBc |
|
|
COMM FEXT (DAC to ADC) |
–75 dBc |
|
|
DIFF NEXT (DAC to ADC) |
–80 dBc |
|
|
COMM NEXT (DAC to ADC) |
–75 dBc |
|
|
CMRR |
–35 dB(2) |
|
|
DIFF RL |
–15 dB |
|
|
COMM RL |
–12 dB |
|
|
Power at BGA footprint |
2 dBm |
|
|
Notes: 1.Refer to Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) [Ref 5] for maximum bandwidth of target device. |
||