The simplest bidirectional topography is point to point. That is, there are two transceivers connected by a transmission line. Because bidirectional interfaces need to operate equally well in both directions, symmetry of the topography is desirable. While asymmetrical topographies can be designed with reasonably good signal integrity, the easiest way to ensure good signal integrity is to keep the topography symmetrical. Thus any termination used on one side of the link should also be used on the other side of the link. Series termination (This Figure) is rarely appropriate for bidirectional interfaces as incoming signals are attenuated by the series resistor of the receiving transceiver. Parallel termination (This Figure) almost always achieves better signal levels at both receivers. Controlled-impedance drivers, whether crudely controlled in the form of a weak LVCMOS driver or adaptively controlled in the form LVDCI or HSLVDCI, also can have good results as shown in This Figure (implemented with a low-drive strength LVCMOS driver). Always use IBIS simulation to determine the optimal termination resistor value, VTT voltage level and VRP reference resistor values for these terminations.
In general, parallel resistive termination (RP) has a value equal to the characteristic impedance Z0 of the transmission line it is terminating. Some interfaces, such as DDR2 memory interfaces, use 75W termination resistors instead of 50W in an effort to open the data eye. In this case, the trade-off is eye height against a small amount of signal reflection from the impedance discontinuity. Controlled-impedance drivers are typically tuned such that the driver output impedance (RO) is equal to the characteristic impedance (Z0) of the transmission line it is terminating.
Assuming transmission lines with 50W characteristic impedance and a driver output impedance of 25W, 50W parallel terminations are appropriate (This Figure). Controlled-impedance drivers, whether implemented with DCI or with weak LVCMOS drivers, should be sized to have an output impedance (RO) of 50W. An example of the use of a controlled-impedance driver would be the LVDCI_15 I/O standard. Weak LVCMOS drivers of 6 mA to 8 mA drive strength have an output impedance approximately equal to 50W (This Figure).
Parallel terminations have the best performance when VTT (the voltage source connected to the parallel termination resistor) is equal to half of the signaling voltage, since this is typically the center voltage of the data eye. For 2.5V signals (VCCO = 2.5V), VTT is ideally 1.25V. In cases where this voltage is not available, it is advisable to use a Thevenin parallel termination. Thevenin parallel termination consists of a voltage divider with a parallel resistance equal to the characteristic impedance of the transmission line (50W in most cases). The divided voltage point is designed to be at VTT. This Figure illustrates a Thevenin parallel termination powered from 2.5V VCCO, made up of two 100W resistors, resulting in a VTT of 1.25V and a parallel equivalent resistance (RPEQ) of 50W.
Parallel termination can be less desirable than series termination or controlled-impedance drivers because it dissipates more power. This trade-off must be weighed against other trade-offs to determine the optimum termination topography for an interface.
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X-Ref Target - Figure 10-10 
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Table: Example I/O Interface Types for Bidirectional Point-to-Point I/O Topographies lists example I/O interface types that can be used with the bidirectional point-to-point topography.
LVTTL and LVCMOS do not specify any canonical termination method. Series termination is not recommended for bidirectional interfaces. Parallel termination and weak drivers, however, are both appropriate.
LVDCI and HSLVDCI both implicitly use controlled-impedance driver termination.
HSTL Class II specifies parallel termination at both transceivers. The termination voltage VTT is defined as half of the supply voltage VCCO. The designer can elect either not to use termination at all or to use a different termination. It is up to the designer to verify through simulation and measurement that the signal integrity at the receiver is adequate.
The JEDEC specifications for SSTL provide examples of both series termination and parallel termination. The termination voltage VTT is defined as half of the supply voltage VCCO. While the specification document provides examples depicting series termination at the drivers, it is important to note that the purpose of this is to attempt to match the impedance of the driver with that of the transmission line. Because the UltraScale architecture SSTL drivers target to have output impedances close to 40–50W, better signal integrity can be achieved without any external source-series termination. When possible, it is a better starting point to consider the use of the 3-state DCI I/O standards (“T_DCI”), which provide internal parallel termination resistors that are only present when the output buffer is in 3-state. It is up to the designer to carefully choose the I/O standard(s) at the AMD device, drive strengths, and on-die termination (ODT) options at the other device(s) in the interface (usually DRAM ICs) and termination topography though careful simulation and measurement. See the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 10] for more details on the available I/O standards and options.