•PCB and package skew between the TX/RX and clock should be within ±100 ps.
•A level shifter must be implemented if using a CAN PHY that operates at a voltage higher than VCCO_PSIO, e.g., 5.0V.
•PCB and package skew between the TX/RX and clock should be within ±100 ps.
•A level shifter must be implemented if using a CAN PHY that operates at a voltage higher than VCCO_PSIO, e.g., 5.0V.