Capacitor Mounting Inductance

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

Capacitor mounting refers to the capacitor's solder lands on the PCB, the trace (if any) between the land and via, and the via.

The vias, traces, and capacitor mounting pads of a 2-terminal capacitor contribute inductance between 300 pH to 4 nH depending on the specific pad routing, via structure and PCB stackup.

Because the current path’s inductance is proportional to the loop area the current traverses, it is important to minimize this loop size. The loop consists of the path through one power plane, up through one via, through the connecting trace to the land, through the capacitor, through the other land and connecting trace, down through the other via, and into the other plane, as shown in This Figure.

Figure 11-6:      Example Cutaway View of PCB with Capacitor Mounting

X-Ref Target - Figure 11-6

ug583_c3_06.jpg

A connecting trace length has a large impact on the mounting’s parasitic inductance and if used, should be as short and wide as possible. When possible, a connecting trace should not be used and the via should butt up against the land. Placing vias to the side of the capacitor lands or doubling the number of vias, further reduces the mounting’s parasitic inductance.

Some PCB manufacturing processes allow via-in-pad geometries, an option for reducing parasitic inductance. Using multiple vias per land is important with ultra-low inductance capacitors, such as reverse aspect ratio capacitors that place wide terminals on the sides of the capacitor body instead of the ends.

PCB layout engineers often try to squeeze more parts into a small area by sharing vias among multiple capacitors. This technique should not be used under any circumstances. PDS improvement is very small when a second capacitor is connected to an existing capacitor’s vias. For a larger improvement, optimize the total number of capacitors and improve the mounting via inductance path.

The capacitor mounting (lands, traces, and vias) typically contributes about the same amount or more inductance than the capacitor's own parasitic self-inductance. If the mounting via structure is not optimized, the capacitor might not be effective at all to PDS.