Capacitor Parasitic Inductance

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

The capacitance value is often considered to be a capacitors’s most important characteristic. In power system applications, the parasitic inductance (ESL) has the same or greater importance. Capacitor package dimensions (body size) determine the amount of parasitic inductance. Physically small capacitors usually have lower parasitic inductance than physically large capacitors.

Requirements for choosing decoupling capacitors:

For a specific capacitance value, choose the smallest package available.

- or -

For a specific package size (essentially a fixed inductance value), choose the highest capacitance value available in that package.

Surface-mount chip capacitors are the smallest capacitors available and are a good choice for discrete decoupling capacitors:

For values from 100 µF to very small values such as 0.01 µF, ceramic X7R or X5R type capacitors are usually used. These capacitors have a low parasitic inductance and a low ESR, with an acceptable temperature characteristic.

For larger values, such as 47 µF to 1000 µF, tantalum capacitors are usually used. These capacitors have a low parasitic inductance and a medium ESR, giving them a low Q factor and consequently a very wide range of effective frequencies.

If tantalum capacitors are not available or cannot be used, low-ESR, low-inductance electrolytic capacitors can be used, provided they have comparable ESR and ESL values. Other new technologies with similar characteristics are also available (Os-Con, POSCAP, and Polymer-Electrolytic SMT). Electrolytic or tantalum capacitors are generally part of the voltage regulator design. They are considered as part of the voltage regulator control loop and should be co-designed with the voltage regulator or control firmware setting. The ESR of these capacitors sets the limit of switching regulator ripple and switching noise along with regulator FET and output inductor design.

A real capacitor of any type then not only has capacitance characteristics but also inductance and resistance characteristics. This Figure shows the parasitic model of a real capacitor. A real capacitor should be treated as an RLC circuit (a circuit consisting of a resistor (R), an inductor (L), and a capacitor (C), connected in series).

Figure 11-3:      Parasitics of a Real, Non-Ideal Capacitor

X-Ref Target - Figure 11-3

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This Figure shows a real capacitor’s impedance characteristic. Overlaid on this plot are curves corresponding to the capacitor’s capacitance and parasitic inductance (ESL). These two curves combine to form the RLC circuit’s total impedance characteristic, softened or sharpened by the capacitor’s ESR.

Figure 11-4:      Contribution of Parasitics to Total Impedance Characteristics

X-Ref Target - Figure 11-4

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As capacitive value is increased, the capacitive curve moves down and left. As parasitic inductance is decreased, the inductive curve moves down and right. Because parasitic inductance for capacitors in a specific package is fixed, the inductance curve for capacitors in a specific package remains fixed.

As different capacitor values are selected in the same package, the capacitive curve moves up and down against the fixed inductance curve, as shown in This Figure.

Figure 11-5:      Effective Frequency Example

X-Ref Target - Figure 11-5

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The low-frequency capacitor impedance can be reduced by increasing the value of the capacitor; the high-frequency impedance can be reduced by decreasing the inductance of the capacitor. While it might be possible to specify a higher capacitance value in the fixed package, it is not possible to lower the inductance of the capacitor (in the fixed package) without putting more capacitors in parallel. Using multiple capacitors in parallel divides the parasitic inductance, and at the same time, multiplies the capacitance value. This lowers both the high and low frequency impedance at the same time.