To perform the decoupling function, capacitors should be close to the device being decoupled.
Increased spacing between the FPGA and decoupling capacitor increases the current flow distance in the power and ground planes, and it often increases the current path’s inductance between the device and the capacitor.
The inductance of this current path (the loop followed by current as it travels from the VCC side of the capacitor to the VCC pin[s] of the FPGA, and from the GND pin[s] of the FPGA to the GND side of the capacitor[s]), is proportional to the loop area. Inductance is decreased by decreasing the loop area.
Shortening the distance between the device and the decoupling capacitor reduces the inductance, resulting in a less impeded transient current flow. Because of typical PCB dimensions, this lateral plane travel tends to be less important than the phase relationship between the FPGA noise source and the mounted capacitor.
The phase relationship between the FPGA’s noise source and the mounted capacitor determines the capacitor’s effectiveness. For a capacitor to be effective in providing transient current at a certain frequency (for example, the capacitor’s resonant frequency), the phase relationship, based on the distance travelled by the current from the FPGA to the capacitor, must be within a fraction of the corresponding period.
The capacitor’s placement determines the length of the transmission line interconnect (in this case, the power and ground plane pair) between the capacitor and FPGA. The propagation delay of this interconnect is the key factor.
FPGA noise falls into certain frequency bands, and different sizes of decoupling capacitors take care of different frequency bands. Thus, capacitor placement requirements are determined by each capacitor’s effective frequency.
When the FPGA initiates a current demand change, it causes a small local disturbance in the PDS voltage (a point in the power and ground planes). Before it can counteract this, the decoupling capacitor must first sense a voltage difference.
A finite time delay occurs between the start of the disturbance at the FPGA power pins and the point when the capacitor senses the disturbance.
The dielectric is the substrate of the PCB where the power planes are embedded.
Another delay of the same duration occurs when the compensation current from the capacitor flows to the FPGA. For any transient current demand in the FPGA, a round-trip delay occurs before any relief is seen at the FPGA.
•Negligible energy is transferred to the FPGA with placement distances greater than one quarter of a demand frequency’s wavelength.
•Energy transferred to the FPGA increases from 0% at one-quarter of a wavelength to 100% at zero distance.
•Energy is transferred efficiently from the capacitor to the FPGA when capacitor placement is at a fraction of a quarter wavelength of the FPGA power pins. This fraction should be small because the capacitor is also effective at some frequencies (shorter wavelengths) above its resonant frequency.
One-tenth of a quarter wavelength is a good target for most practical applications and leads to placing a capacitor within one-fortieth of a wavelength of the power pins it is decoupling. The wavelength corresponds to the capacitor's mounted resonant frequency, FRIS .
When using large numbers of external termination resistors or passive power filtering for transceivers, priority should be given to these over the decoupling capacitors. Moving away from the device in concentric rings, the termination resistors and transceiver supply filtering should be closest to the device, followed by the smallest-value decoupling capacitors, then the larger-value decoupling capacitors.