DDR3 SDRAM Clock Fly-by Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

Inherent to fly-by topology, the timing skew between the clock and dqs signals is deskewed by the write leveling feature on DDR3 SDRAM (This Figure).

Figure 2-30:      Clock Fly-by Termination for DDR3 SDRAM

X-Ref Target - Figure 2-30

ug583_c2_21.jpg

Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals shows the DDR3 SDRAM impedance, length, and spacing guidelines for clock signals.

Table 2-22:      DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

L3

L4
(To RTT)

Units

Trace type

Stripline

Stripline

Stripline

Stripline

Stripline

Clock differential impedance ZDIFF

86±10%

76±10%

86±10%

90±10%

76±10%

W

Trace width/space/width

4.0/4.0/4.0

6.0/6.0/6.0

4.0/4.0/4.0

4.0/5.0/4.0

6.0/6.0/6.0

mil

Trace length

0.0~1.5(1)(2)

0.0~4.0

0.0~0.1

0.35~0.75

0~1.0

inches

Spacing in address, command, and control signals (minimum)

8.0

20(2)

8.0

20

20

mil

Spacing to other group signals (minimum)

8.0

30

8

30

30

mil

Maximum PCB via count per signal

7

Notes:

1.See item 2 in General Memory Routing Guidelines.

2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 30.