DDR3 SDRAM Data Signals Point-to-Point

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

This Figure shows the data signals (DQ, DM, and DQS) point-to-point for DDR3 SDRAM.

Figure 2-31:      Data Signals Point-to-Point for DDR3 SDRAM

X-Ref Target - Figure 2-31

ug583_c2_22.jpg

Table: DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals shows the DDR3 SDRAM impedance, length, and spacing guidelines for data signals.

Table 2-23:      DDR3 SDRAM Impedance, Length, and Spacing Guidelines for Data Signals

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

Units

Trace type

Stripline

Stripline

Stripline

dq single-ended impedance Z0

50±10%

39±10%

50±10%

W

dqs differential impedance ZDIFF

86±10%

76±10%

86±10%

W

Trace width (nominal)

4.0

6.0

4.0

mil

Differential trace width/space/width

4.0/4.0/4.0

6.0/6.0/6.0

4.0/4.0/4.0

mil

Trace length (nominal)

0.0~1.5(1)(2)

0.0~5.0

0.0~0.1

inches

Spacing in byte (minimum)

4.0

8.0(2)

4.0

mil

Spacing byte to byte (minimum)

4.0

20

4.0

mil

dq to dqs spacing (minimum)

4.0

20

8.0

mil

Spacing to other group signals (minimum)

8.0

30

30

mil

Maximum PCB via count

2

Notes:

1.See item 2 in General Memory Routing Guidelines.

2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 12.0.