DDR3 SDRAM Interface Signal Description

Clock Signals

ck_p/n[1:0]

Differential clock

Control Signals

cke[1:0]

Clock enable.

cs_n[1:0]

Chip select

odt[1:0]

On-die termination enable

reset_n

See reset_n

Address Signals

a[15:0]

Memory address bus

ba[2:0]

Bank address

Command Signals

ras_n

Row address select

cas_n

Column address select

we_n

Write enable

Data Signals

dq[79:0]

Data bus

dqs_p/n[9:0]

Differential data strobe

dm[9:0]

Data mask

Other Signals

VRP (PL)

240W to GND

ZQ (PS)

240W to GND

Notes:

1.Actual signal list might vary based on configuration.