DDR3 SDRAM Routing Constraints

UltraScale Architecture PCB Design User Guide (UG583)
Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

There are two constraints requirements for each signal group in the DDR3 memory interface:

•Total length/delay constraints

•Skew constraints

The total length/delay constraints are shown in Table: DDR3 SDRAM Total Length/Delay Constraints.

Table 2-24:      DDR3 SDRAM Total Length/Delay Constraints

Signal Group

Reference Figure

Maximum Length/Delay Constraints

Address/command/control: x1/x2/x3/x4/x5/x6/x7/x8/x9
(includes package routing P0)

This Figure

6.15/6.9/7.65/8.4/9.15/9.9/10.65/11.4/12.15 inches

1042/1169/1296/1423/1550/1678/1805/1932/2110 ps

Data Signals P0+L0+L1+L2

This Figure

7.0 inches, 1186 ps

The skew constraints are shown in Table: DDR3 SDRAM Data Group Skew Constraints and Table: DDR3 SDRAM Address, Command, and Control Skew Constraints.

Table 2-25:      DDR3 SDRAM Data Group Skew Constraints

Signal Group

Skew Constraints (ps)

Skew Constraints (mil)

Data(1) to DQS

±10

±58

dqs_p and dqs_n

2

12

CK to DQS

–149 to 1,796

–879 mil to 10.6 inches

Notes:

1.The data group includes dq and dm.

2.Delays are based on 169.5 ps/in. See item 8 in General Memory Routing Guidelines.

3.For skew specifications, refer to the General Memory Routing Guidelines items 3–8.

The address, command, and control clock group skew constraints are listed in Table: DDR3 SDRAM Address, Command, and Control Skew Constraints.

Table 2-26:      DDR3 SDRAM Address, Command, and Control Skew Constraints

Signal

Signal Segment

Skew Constraints (ps)

Skew Constraints (mil)

Address/command/control(1) to CK

UltraScale device to each memory device

±8 ps

±47

ck_p and ck_n

UltraScale device to each memory device

2

12

Notes:

1.The signal reset_n is not required to meet the skew constraints in this table.

2.For skew specifications, refer to the General Memory Routing Guidelines items 3–8.

 

IMPORTANT:   FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.