DDR3/DDR4 DIMM Clock Point-to-Point Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID: UG583
Release Date: 2023-11-14
Revision: 1.27 English

This Figure and Table: Impedance, Length, and Spacing Guidelines for DIMM Clock Signals define the routing topology and guidelines for DDR3/DDR4 DIMM clock signals.

Figure 2-32: CK Point-to-Point Routing for DDR3/DDR4 DIMM Topology
X-Ref Target - Figure 2-32

Table 2-27: Impedance, Length, and Spacing Guidelines for DIMM Clock Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	Units
Trace type	Stripline	Stripline	–
Differential impedance Z₀	86±10%	66±10%	W
Trace width/space/width	4.0/4.0/4.0	8.0/8.0/8.0	mil
Trace length	0.0~1.5⁽¹⁾⁽²⁾	0.0~4.0	inches
Spacing to address, command, and control signals (minimum)	8.0	20⁽²⁾	mil
Spacing to other group signals (minimum)	8.0	30	mil
Maximum PCB via count	2		–
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 30.