DDR3/DDR4 DIMM Control, Command, and Address Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

This Figure, This Figure, Table: Impedance, Length, and Spacing Guidelines for One-Slot DIMM Address, Command, and Control Signals, and Table: Impedance, Length, and Spacing Guidelines for DIMM Data Signals define the routing topologies and routing guidelines for DDR3/DDR4 DIMM address, command, and control signals. Place four 0402 1.0 µF capacitors in the CMD/CTRL pin area of the DIMM connector. All capacitors should connect from V_CCO to GND.

Figure 2-33: CTRL Point-to-Point Routing for DDR3/DDR4 DIMM Topology
X-Ref Target - Figure 2-33

Figure 2-34: CMD/ADDR Fly-by Routing for DDR3/DDR4 DIMM Topology
X-Ref Target - Figure 2-34

Note: The Zynq UltraScale+ MPSoC DDR interface does not support dual-DIMM topologies.

Table 2-28: Impedance, Length, and Spacing Guidelines for One-Slot DIMM Address, Command,
and Control Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	Units
Trace type	Stripline	Stripline	–
Single-ended impedance Z₀	50±10%	39±10%	W
Trace width	4.0	6.0	mil
Trace length	0.0~1.5⁽¹⁾⁽²⁾	0.0~4.0	inches
Spacing in address, command, and control signals (minimum)	4.0	12⁽²⁾	mil
Spacing to clock signals (minimum)	8.0	20	mil
Spacing to other group signals (minimum)	8.0	30	mil
Maximum PCB via count	2		–
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 16.0.

Table 2-29: Impedance, Length, and Spacing Guidelines for Two-Slot DIMM Address, Command,
and Control Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DIMM to DIMM)	Units
Trace type	Stripline	Stripline	Stripline	–
Single-ended impedance Z₀	50±10%	34±10% addr/cmd 39±10% ctrl	34±10% addr/cmd 39±10% ctrl	W
Trace width	4.0	6.9 addr/cmd 6.0 ctrl	6.9 addr/cmd 6.0 ctrl	mil
Trace length	0.0~1.5⁽¹⁾⁽²⁾	0.0~4.0	<0.5	inches
Spacing in address, command, and control signals (minimum)	4.0	12.0 ctrl, 13.8 addr/cmd⁽²⁾	12.0 ctrl, 13.8 addr/cmd	mil
Spacing to clock signals (minimum)	8.0	20	8.0	mil
Spacing to other group signals (minimum)	8.0	30	30	mil
Maximum PCB via count	Addr/cmd: 3 Ctrl: 2			–
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 18.0 ctrl, and 20.7 addr/cmd.