DDR3/DDR4 DIMM Data (DQ and DQS) Routing

UltraScale Architecture PCB Design User Guide (UG583)

Document ID: UG583
Release Date: 2023-11-14
Revision: 1.27 English

This Figure, This Figure, and Table: Impedance, Length, and Spacing Guidelines for DIMM Data Signals define routing topologies and guidelines for DDR3/DDR4 DIMM data routing.

Figure 2-36: DQS Fly-by Routing for DDR3/DDR4 DIMM Topology
X-Ref Target - Figure 2-36

Note: The Zynq UltraScale+ MPSoC DDR interface does not support dual-DIMM topologies.

Figure 2-37: DQ Fly-by Routing for DDR3/DDR4 DIMM Topology
X-Ref Target - Figure 2-37

Note: The Zynq UltraScale+ MPSoC DDR interface does not support dual-DIMM topologies.

Table 2-30: Impedance, Length, and Spacing Guidelines for DIMM Data Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DIMM to DIMM)	Units
Trace type	Stripline	Stripline	Stripline	–
dq single-ended impedance Z₀	50±10%	39±10%	39±10%	W
dqs differential impedance Z_DIFF	86	66	66	W
dq trace width (nominal)	4.0	6.0	6.0	mil
Dqs differential trace width/space/width	4.0/4.0/4.0	8.0/8.0/8.0	8.0/8.0/8.0	mil
Trace length	0.0~1.5⁽¹⁾⁽²⁾	0.0~4.0	£0.5	inches
Spacing in byte (minimum)	4.0	15⁽²⁾	15	mil
Spacing byte to byte (minimum)	4.0	30	30	mil
dq to dqs spacing (minimum)	4.0	21	21	mil
Spacing to other group signals (minimum)	8.0	30	30	mil
Maximum PCB via count	2 for 1 DIMM, 3 for two DIMMs			–
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 20.0.