For the case of two dual in-line memory modules (DIMMs), each DIMM has its own set of point-to-point clock and control signals, while data, command, and address route to both DIMMs in a fly-by topology.
IMPORTANT: The Processing System (PS) does not support multiple DIMMs.
IMPORTANT: This Figure, This Figure, and This Figure show configurations with multiple DIMMs. To reduce the effect of SI reflections, always place DIMM #0 on the furthest connector from the FPGA. DIMM #1, if present, should be placed on the connector nearest to the FPGA.
This Figure, This Figure, and This Figure show configurations with multiple DIMMs. To reduce the effect of SI reflections, always place DIMM #0 on the furthest connector from the FPGA. DIMM #1, if present, should be placed on the connector nearest to the FPGA.