DDR4 SDRAM Clock Fly-By and Clamshell Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

Inherent to fly-by topology, the timing skew between the clock and dqs signals is deskewed by the write-leveling feature on DDR4 SDRAM (This Figure).

Figure 2-25: Clock Fly-by Termination for DDR4 SDRAM
X-Ref Target - Figure 2-25

Table: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals shows the DDR4 SDRAM impedance, length, and spacing guidelines for clock signals.

Table 2-14: DDR4 SDRAM Impedance, Length, and Spacing Guidelines for Clock Signals
Parameter	L0 (Device Breakout)	L1 (Main PCB)	L2 (DRAM Breakout)	L3	L4 (To R_TT)	Units
Trace type	Stripline	Stripline	Stripline	Stripline	Stripline	–
Clock differential impedance Z_DIFF	86±10%	76±10%	86±10%	90±10%	76±10%	W
Trace width/space/width	4.0/4.0/4.0	6.0/6.0/6.0	4.0/4.0/4.0	4.0/5.0/4.0	6.0/6.0/6.0	mil
Trace length	0.0~1.5⁽¹⁾⁽²⁾	0.0~4.0	0.0~0.1	0.35~0.75	0~1.0	inches
Spacing in address, command, and control signals (minimum)	8.0	20⁽²⁾	8.0	20	20	mil
Spacing to other group signals (minimum)	8.0	30	8.0	30	30	mil
Maximum PCB via count per signal	7					–
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 30.

For DDR4 SDRAM clamshell topology, an alternating fly-by topology is recommended for clock signals. The alternating layer routing properly balances the signal loads at each memory device. As depicted in Table: Impedance, Length, and Spacing Guidelines for One-Slot DIMM Address, Command, and Control Signals with the FPGA located at the top layer, the inner layer routing to top layer devices 1, 3, 5, 7, and 9 is closer to the top layer, while the inner layer routing to bottom layer devices 2, 4, 6, and 8 is closer to the bottom layer.

Figure 2-26: Clock Topology for DDR4 SDRAM Clamshell
X-Ref Target - Figure 2-26

Note: The end-termination components can be located on either the top or bottom layer.

Table: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Clock Signals shows the DDR4 SDRAM clamshell impedance, length, and spacing guidelines for clock signals. Note the extra length of the L2 segment.

Table 2-15: DDR4 SDRAM Clamshell Impedance, Length, Width, and Spacing Guidelines for Clock Signals
Parameter	L0 FPGA Breakout	L1	L2	L3	L4	L5	L6 V_TT Stub	Units
Layer (recommended)	Upper inner	Upper inner	Lower inner	Upper inner	Top	Bottom	Bottom
Differential impedance Z₀	86	76	90	90	86	86	76	W
Length	0.0~1.5⁽¹⁾	0.0~4.0	L3+0.2	0.45~0.85	For mirrored case, L4 = L5; for non- mirrored case, make as short as possible		£1.0	inch
Width/space/ width	4.0/4.0/4.0	6.0/6.0/6.0	4.0/5.0/4.0	4.0/5.0/4.0	4.0/4.0/4.0	4.0/4.0/4.0	6.0/6.0/6.0	mil
Spacing to addr/cmd/ctrl	8.0	20⁽¹⁾	20	20	20	20	20	mil
Spacing to other groups	8.0	30	30	30	30	30	30	mil
Notes: 1.If greater than 1.5 inches is needed in the breakout area, change L1 spacing to 30.

IMPORTANT: Add as many ground vias as possible to help avoid crosstalk issues. See item 20 in General Memory Routing Guidelines.