DDR4 SDRAM Interface Signal Description

Clock Signals

ck_t, ck_c

Differential clock

Address and Command Signals

a[17,13:0]

Address inputs

ras_n/a[16]

Row address strobe, address bit 16

cas_n/a[15]

Column address strobe, address bit 15

we_n/a[14]

Write enable, address bit 14

bg[1:0]

Bank group inputs

ba[1:0]

Bank address inputs

act_n

Activation command input

par

Command and address parity input

Control Signals

cke

Clock enable

cs_n[3:0]

Chip select

odt

On-die termination enable

reset_n

See reset_n

Data Signals

dq[79:0]

Data input/output

dqs_t/dqs_c[9:0]

Data strobe (differential)

dm_n/dbi_n

Data mask and data bus inversion

Other Signals

TEN

Test connectivity mode. CMOS level. Connect 500W resistor to ground at memory devices.

alert_n

see alert_n

VRP (PL)

240W to GND

ZQ (PS)

240W to GND

Notes:

1.Actual signal list might vary based on configuration.