There are two constraints requirements for each signal group in the DDR4 DIMM interface:
•Total length/delay constraints
•Skew constraints
The total length/delay constraints are shown in Table: DDR4 DIMM Total Length/Delay Constraints.
The skew constraints are listed in Table: DDR4 DIMM Skew Constraints and Table: DDR4 DIMM Address, Command, and Control Skew Constraints.
Signal Group |
Skew Constraints (ps) |
Skew Constraints (mil) |
---|---|---|
Data(1) to DQS |
±10 |
±58 |
dqs_p and dqs_n |
2 |
12 |
CK to DQS(2) |
±150 |
±885 |
Notes: 1.The data group includes dq and dm_n/dbi_n. 2.Clock to DQS constraints should be from the UltraScale device to the DIMM. 3.Delays are based on 169.5 ps/in. See item 8 in General Memory Routing Guidelines. 4.For skew specifications, refer to the General Memory Routing Guidelines items 3–8. |
Signal |
Signal Segment |
Skew Constraints (ps) |
Skew Constraints (mil) |
---|---|---|---|
Address/command/ control(1) to CK |
UltraScale device to each memory device |
±8 ps |
±47 |
ck_p and ck_n |
UltraScale device to each DIMM |
2 |
12 |
Notes: 1.The signal reset_n is not required to meet the skew constraints in this table. 2.For skew specifications, refer to the General Memory Routing Guidelines items 3–8. |
IMPORTANT: FPGA package flight times must be included in both total length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values. Memory device package flight times do not need to be factored in because their variances have been accounted for in these guidelines.