ECC Connection Rules for DDR4 SDRAM

For DDR4 interfaces when using ECC with x16 components, the lower data byte (DQ[7:0]) of the last component must be connected to the ECC byte of the controller. If the lower data byte is not connected and instead the upper data byte is used, the per-DRAM addressability feature does not function correctly, which results in V_REF calibration errors.  This results in FSBL hangs for Zynq UltraScale+ MPSoC based designs.  Functionality is not impacted for soft controller designs because V_REF calibration is not used. However, if V_REF calibration is enabled, it results in functional errors.

For DDR4-based interfaces, the unused upper data byte must be connected as follows (unless explicitly stated otherwise in the memory vendor's datasheet):

•DQ[15:8] can be left floating.

•UDM or UDM_n/UDBI_n terminate to V_DD with a pull-up resistor £ 4.7 KW.

•UDQS or UDQS_t terminate to V_DD with a pull-up resistor £ 4.7 KW.

•UDQS# or UDQS_c terminate to V_SS with a pull-down resistor £ 4.7 KW.