This Figure shows a die-level floorplan for a design utilizing the VU125 in the C2104 package. This design includes several memory interfaces, a 100G Ethernet interface, an Interlaken 12x12.5G interface, and a Tandem PCIe interface. The bank(s) that each interface utilizes are shown color-coordinated, along with the relevant block locations.
This Figure shows how the various interfaces can migrate into a VU7P device that is also in the C2104 package. All interfaces can and must map to the same banks (and corresponding pins), as well as adhering to all block location requirements such as MAC, Interlaken, and PCIe banks needing to be within one row of their respective locations on the die. This particular example is reasonably straightforward in that the two device floorplans are very close to equal, with similar bank and block locations along with similar SLR boundaries.
