Two topology types are supported for DDR4 SDRAM: fly-by, and clamshell. The fly-by topology (This Figure) consists of all memory devices on one layer, usually in-line. This type of topology is generally easier to route and can offer the best signal integrity, but can take up precious board real estate.
Clamshell topology (This Figure) requires more intricate routing, but is optimal for designs where board space is at a premium.
IMPORTANT: Clamshell is a supported DDR4 SDRAM topology in the MIG tool and is selectable for Programmable Logic banks only. The PS in the Zynq UltraScale+ MPSoC does not have a selectable clamshell configuration option. However, the PS can be configured as clamshell if set up as a dual-rank configuration with the first rank on the top layer, and the second rank mirrored on the bottom layer. When utilizing this topology within the AMD Vivado™ tools, refer to the Clamshell Topology section in UltraScale Architecture-Based FPGAs Memory IP Product Guide (PG150) [Ref 13] for additional information.
