1.Include package delay in routing constraints when determining signal trace lengths. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values.
2.UltraScale device breakout specifications assume two signal routes between pads. If routing one signal between pads, traces can be 39W instead of 50W. To minimize coupling, minimize trace lengths as much as possible when routing two signals between pads.
3.Signal-to-signal skew constraints in this chapter are presented in the form X to Y, where the Y signal is the reference point. Within the specified constraint, signal X can be shorter or longer than signal Y. If signal X is part of a bus, then the shortest and longest signals in the bus must be within the listed specification. If the Y signal is a differential clock or signal group, then Y is defined as the mid-point between shortest and longest signals in the pair/group.
Table: Example Signal to Signal Skew Constraint shows an example DQ to DQS signal-to-signal constraint specification. This Figure illustrates an interpretation of the constraint. The shortest DQ in the data bus can be no more than 5 ps ahead of the DQS signal (mid-point of DQS_P and DQS_N), while the longest DQ in the bus can be no more than 5 ps after the DQS signal.
|
Signal Group |
Skew Constraints (ps) |
Skew Constraints (mil) |
|---|---|---|
|
DQ to DQS |
±5 |
±29 |
4.Differential signal group skew constraints in this chapter are presented in the form X. The difference between the longest signal and the shortest signal in the X group must be no greater than the specified constraint.
Table: Example Signal Group Skew Constraint shows an example clock group constraint specification. This Figure illustrates an interpretation of the constraint. The difference in delay between the longest clock signal in the bus and the shortest clock in the bus can be no greater than 2 ps.
|
Signal Group |
Skew Constraints (ps) |
Skew Constraints (mil) |
|---|---|---|
|
ck_p and ck_n |
2 |
12 |
5.The CK to DQS specification for DDR3 and DDR4 component interfaces encompasses a wide range, as shown in Table: Example CK to DQS Skew Constraint. The wide range is to ensure that proper write leveling can take place at all memory devices, from the first in the chain to the last.
|
Signal Group |
Skew Constraint (ps) |
Skew Constraint (mil) |
|---|---|---|
|
CK to DQS |
–149 to 1796 |
–879 to 10,600 |
The UltraScale device memory controller can internally delay the DQS line to account for negative skew, which helps because the CK line encounters more capacitive load than each individual DQS pair because the CK lines touch each memory device in the chain. This slows the CK line relative to each DQS, which only touches one memory device. The specification routes the CK and DQS lines where the skew between CK to DQS is no less than –149 ps from the UltraScale device to the first memory device in the chain and no more than 1796 ps to the furthest memory device in the chain. This is illustrated in This Figure. As long as the first memory device and the last memory device in the chain are bounded by this constraint, all memory devices can be write leveled.
For example, if the DQS delay between the UltraScale device and the first memory device is 200 ps, the clock delay from the UltraScale device to the first memory device should be at least 51 ps (200 ps – 149 ps). If the DQS delay from the UltraScale device to the furthest memory device is 700 ps, the clock delay from the UltraScale device to the last memory device should be less than 2496 ps (700 ps + 1796 ps).
TIP: DIMM guidelines have a much narrower CK to DQS specification because the PCB is only routed from the UltraScale device to the first memory device in the DIMM. The routing from the first memory device to the last memory device is managed by the DIMM.
6.Skew constraints assume the fastest interface speeds. For slower speeds, certain skews can be relaxed. Refer to Memory Derating Tables for derating tables for the various memory interfaces.
7.Skew and length constraints assume a propagation time of 169.5 ps/in based on the stackup shown in Table: Reference Stackup. Maximum trace lengths can be relaxed or tightened depending on the actual propagation time of the board. To convert, multiply the specified trace length by 169.5 ps, then divide by the actual propagation time of the board. See Adjusting for Different Stack-Ups.
8.Trace widths and spacing are based on the stackup shown in Table: Reference Stackup. If another stackup scheme is used, the widths and spacing can be modified to meet the impedance targets. See Adjusting for Different Stack-Ups.
9.DQ and DQS signals in the same byte group should be routed in the same layer from UltraScale device to DRAM/DIMM, except in the breakout areas. Include the data mask (DM) in the byte group as applicable.
10.Do not change layers when routing from one DIMM to the next, if applicable. In addition, for DIMM routing, it is recommended to route data byte groups on the highest signal layers (closest to the DIMM connector) as much as possible, especially for byte groups located near the center of the DIMM.
11.For fly-by routing, address, command, and control signals can be routed on different layers, though it is recommended to use as few as possible. Do not route any individual signal on more than two layers to minimize inductive loops that can lead to crosstalk issues. Any signal layer switching via needs to have one ground via within a 50 mil perimeter range.
12.UltraScale device and memory drive strengths depend on the particular memory standard and memory component(s) being used. Memory guidelines in this document are based on the default standard used by the Memory Interface Generator (MIG).
13.When utilizing the internal VREF, the dedicated VREF pin can be tied to GND with a 500W or 1 kW resistor. Take care to minimize via coupling so as to reduce noise coupling through the VREF pin.
Note: When internal VREF is used, this pin cannot be used as an I/O.
14.If the system clock is connected to a bank that is also used for memory, terminate as shown for LVDS in This Figure with the appropriate pull-up voltage. This termination circuit is necessary because of the different I/O standard of the memory bank (HSTL, SSTL, or POD).
15.Signal lines must be routed over a solid reference plane. Avoid routing over voids (This Figure).
16.Avoid routing over reference plane splits (This Figure).
17.Keep the routing at least 30 mils away from the reference plane and void edges with the exception of breakout regions (This Figure).
18.In the breakout region, route signal lines in the middle of the via void aperture. Avoid routing at the edge of via voids (This Figure).
19.Use chevron-style routing to allow for ground stitch vias. This Figure shows recommended routing for fly-by configurations, while This Figure shows recommended routing to accommodate ground stitch vias in a more congested clamshell configuration.
IMPORTANT: Crosstalk issues leading to data errors can occur with lack of proper ground stitching, especially in areas where there are fewer ground pins, such as near address pins of memory devices.
|
This Figure shows simulated eye diagrams for a DDR4 command/address/control bit with and without ground stitching vias. The simulation on the left shows an eye height of 180 mV with ground stitch vias, while the simulation on the right shows an eye height of only 99 mV when not utilizing ground stitch vias.
20.Add ground vias as much as possible around the edges and inside the device (FPGA, MPSoC, memory component, DIMM) to make a better ground return path for signals and power, especially corners. Corner or edge balls are generally less populated as grounds.
21.For address/command/control VTT termination, every four termination resistors should be accompanied by one 0.1 µF capacitor, physically interleaving among resistors, as shown in This Figure. Refer to the memory vendor’s data sheet for specifications regarding noise limits on the address/command/control VTT lines.
22.For DIMMs, place bypass capacitors near the command/address/control pads to provide extra ground via locations. In addition, the bypass capacitors also provide a lower impedance path from power to ground, which is important because address/command/control pins are referenced to ground on the FPGA and PCB, while they are referenced to power on the DIMM.
23.To optimize the signal routing, the recommendation for one component placement is shown in This Figure.
For five components, the recommendation is shown in This Figure.
