The input circuitry of the single-ended standards fall into two categories: those with fixed input thresholds and those with input thresholds set by the VREF voltage. The use of VREF has three advantages:
•It allows for tighter control of input threshold levels
•It removes dependence on die GND for the threshold reference
•It allows for input thresholds to be closer together, which reduces the need for a large voltage swing of the signal at the input receiver
Two 1.8V I/O standards that illustrate this are LVCMOS18 and SSTL18 Class 1. The thresholds for 1.8V LVCMOS are set at 0.63V and 1.17V (necessitating that the signal at the receiver swing a full 540 mV at minimum to make a logic transition). The thresholds for SSTL18 Class 1 are set at VREF – 0.125V and VREF + 0.125V, or for a nominal VREF of 0.9V, set at 0.775V and 1.025V (necessitating that the signal at the receiver only swing 250 mV at minimum to make a logic transition). This smaller required swing allows for higher frequency of operation in the overall link. A smaller swing at the driver means reduced DC power is required with less transient current. In the UltraScale architecture-based devices, the reference voltage can either be provided using the dedicated VREF pins, or optionally generated internally using the Internal VREF feature. See the SelectIO Resources chapter of the UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 10] for more details on Internal VREF. For more information on VREF decoupling and decoupling of all other supplies, see Power Distribution System in UltraScale Devices.