Isolation Recommendations

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

Incorporating all the following PCB design techniques results in the highest isolation between traces on the PCB. If significant deviation from the guidelines is planned, AMD recommends performing 3D EM analysis of the board structure to verify that performance at the package launch traces is acceptable for the application.

Note:   Separation between traces is not entirely sufficient to achieve the isolation recommendations listed below. The effect of crosstalk rolls off as 1/(1+(s/h)2), where s is trace separation, and h is dielectric thickness. This function does not have a steep roll-off, and because space is limited, other methods must be used to achieve the recommended isolation.

Refer to Table: Signal Integrity Specifications for DAC/ADC Pairs and Clocks for isolation recommendations for ADC and DAC pairs. A number of methods can be used to achieve the best isolation:

Micro vias, 3 dB isolation improvement: Micro vias are preferred over back drilling due to any residual stubbing and the presence of a resonance cavity.

Shorter vias, 1 dB isolation improvement per 5 mil (0.13 mm) length: Vias are a source of crosstalk, which can be minimized by keeping lengths as short as possible.

Differential breakout, 3 dB isolation improvement: Differential breakout, as shown in This Figure, is preferred over single-ended breakout. Single-ended breakout crosstalk is highest within 78 mil (2.0 mm) from the package edge and should be avoided, if possible.

Figure 3-7:      Differential Breakout Example

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X19470-differential-breakout-example.jpg

Guard traces, 10 dB isolation improvement: Separate each P/N pair by a ground guard-band trace that is 2X the layer height. Ensure that the above and below ground planes extend at least 4H away from the edge of each signal trace. Stitch the guard-band trace to ground every 118 mil ± 39 mil (3.0 mm ± 1 mm). All ground stitching should be implemented with through-hole vias. This Figure shows an example of guard-band stitching around P/N pairs.

Figure 3-8:      Example of Ground Stitching around Signal Pairs

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X19471-example-of-ground-stitching-around-signal-pairs.jpg

This Figure shows closer detail of guard traces and ground stitching vias. Ensure to continue ground stitching around the pins of the RFSoC, as shown in Sample Stackup.

Figure 3-9:      Close View of Guard Traces and Ground Stitching

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X19904-close-view-of-guard-traces-and-ground-stitching3.jpg

This Figure shows a cross-section view of the guard traces.

Figure 3-10:      Cross-Section of Guard Traces

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X22756-Cross_Section_of_Guard_Trace.jpg

Via-In-Pad, Plated Over (VIPPO), 5 dB isolation improvement: Plated via-in-pad is preferred over routing a dog-bone trace to a via, because a dog-bone on layer one is subject to more crosstalk from PCB and external sources.