The PS DDR interface includes a feature called address copy to reduce loading on the address/command bus when operating in LPDDR3 mode. A[9:0] are replicated on ACT_N, BG[0], BA[1:0], and A[15:10] to allow fewer loads on the CA bus (Table: LPDDR3 Address Copy).
Table 2-62: LPDDR3 Address Copy
MPSoC Pin
|
DRAM Pin
|
MPSoC Pin Copy
|
DRAM Pin
|
PS_DDR_A0
|
CA0_A
|
PS_DDR_A10
|
CA0_B
|
PS_DDR_A1
|
CA1_A
|
PS_DDR_A11
|
CA1_B
|
PS_DDR_A2
|
CA2_A
|
PS_DDR_A12
|
CA2_B
|
PS_DDR_A3
|
CA3_A
|
PS_DDR_A13
|
CA3_B
|
PS_DDR_A4
|
CA4_A
|
PS_DDR_A14
|
CA4_B
|
PS_DDR_A5
|
CA5_A
|
PS_DDR_A15
|
CA5_B
|
PS_DDR_A6
|
CA6_A
|
PS_DDR_BA0
|
CA6_B
|
PS_DDR_A7
|
CA7_A
|
PS_DDR_BA1
|
CA7_B
|
PS_DDR_A8
|
CA8_A
|
PS_DDR_BG0
|
CA8_B
|
PS_DDR_A9
|
CA9_A
|
PS_DDR_ACT_N
|
CA9_B
|