LPDDR3 SDRAM Address, Command, and Control Point-to-Point Termination

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

With high-speed signaling in LPDDR3 SDRAM, point-to-point topology is used for address, command, and control signals to achieve the best signal integrity in X32 system. Each address, command, and control signal by itself is routed continuously in the same layer from device pin to far-end termination, except in breakout areas. In other words, each individual address, command, or control signal routing is not broken into routings on multiple layers. This Figure shows the address, command, and control point-to-point termination for LPDDR3 SDRAM.

Figure 2-56:      Address, Command, and Control Point-to-Point Termination for LPDDR3 SDRAM

X-Ref Target - Figure 2-56

ug583_c8_30.jpg

Table: LPDDR3 x32 SDRAM Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signal Point-to-Point Connection and Table: LPDDR3 x64 SDRAM Impedance, Length, and Spacing Guidelines for Address and Command Signal Point-to-Point Connection show the LPDDR3 SDRAM impedance, length, and spacing guidelines for address, command, and control signals for x32 and x64 systems, respectively. In the LPDDR3 DRAM package, the vertical pitch is only 0.65 mm. Due to limited space, the trace impedance in L2 could be up to 60W. Address, command, and control signals have on-board termination. There is no on-die termination available. All address, command, and control signals are point-to-point connections for a x32 single-SDRAM system. For a x64 two-SDRAM system, address and command signals are point-to-point connections while control signals including CS, CKE, and ODT are connected from the FPGA to the two SDRAMs in fly-by topology.

Table 2-65:      LPDDR3 x32 SDRAM Impedance, Length, and Spacing Guidelines for Address, Command, and Control Signal Point-to-Point Connection

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

L3
(OBT)

Units

Trace type

Stripline

Stripline

Stripline

Stripline

-

Single-ended impedance Z0

50±10%

39±10%

52±10%

39±10%

W

Trace width (nominal)

4.0

6

3.5

6

mil

Trace length

0.0~0.55

1.0~4.0

0.0~0.2

0.0~0.5

inch

Spacing in cmd/addr/ctrl signals (minimum)

4.0

8.0

4.0

4.0

mil

Spacing to clock signals (minimum)

8.0

20

8.0

20

mil

Spacing to other group signals (minimum)

8.0

30

8.0

30

mil

Maximum PCB via count

3

mil

Notes:

1.See item 2 in General Memory Routing Guidelines.

Table 2-66:      LPDDR3 x64 SDRAM Impedance, Length, and Spacing Guidelines for Address and Command Signal Point-to-Point Connection

Parameter

L0
(Device Breakout)

L1
(Main PCB)

L2
(DRAM Breakout)

L3
(OBT)

Units

Trace type

Stripline

Stripline

Stripline

Stripline

-

Single-ended impedance Z0

50±10%

39±10%

52±10%

39±10%

W

Trace width (nominal)

4.0

6

3.5

6

mil

Trace length

0.0~0.55

1.0~4.0

0.0~0.2

0.0~0.5

inch

Spacing in cmd/addr/ctrl signals (minimum)

4.0

8.0

4.0

4.0

mil

Spacing to clock signals (minimum)

8.0

20

8.0

20

mil

Spacing to other group signals (minimum)

8.0

30

8.0

30

mil

Maximum PCB via count

3

mil

Notes:

1.See item 2 in General Memory Routing Guidelines.

2.Control signals (CS/CKE/ODT) are routed under different constraints.