This Figure shows the clock point-to-point termination for LPDDR3 SDRAM.
Table: LPDDR3 x32 SDRAM System Impedance, Length, and Spacing Guidelines for Clock Signals and Table: LPDDR3 x64 SDRAM System Impedance, Length, and Spacing Guidelines for Clock Signals show the LPDDR3 SDRAM impedance, length, and spacing guidelines for clock signals for x32 and x64 systems, respectively. For LPDDR3 SDRAM, clock signals have on-board termination. There is no on-die termination available for clock signals. For both x32 and x64 systems, clock signals are point-to-point connections to achieve the highest operation frequency.
|
Parameter |
L0 |
L1 |
L2 |
L3 |
Units |
|---|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
- |
|
Single-ended impedance Z0 |
50±10% |
39±10% |
52±10% |
39±10% |
W |
|
Differential impedance Z0d |
86±10% |
76±10% |
88±10% |
76±10% |
W |
|
Trace width/spacing/width (nominal) |
4.0/4.0/4.0 |
6.0/6.0/6.0 |
3.5/3.25/3.5 |
6.0/6.0/6.0 |
mil |
|
Trace length |
0.0~0.55 |
1.0~4.0 |
0.0~0.3 |
0.0~0.5 |
inch |
|
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
20 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
30 |
mil |
|
Maximum PCB via count |
3 |
mil |
|||
|
Notes: 1.See item 2 in General Memory Routing Guidelines. |
|||||
|
Parameter |
L0 |
L1 |
L2 |
L3 |
Units |
|---|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
- |
|
Single-ended impedance Z0 |
50±10% |
39±10% |
52±10% |
39±10% |
W |
|
Differential impedance Z0d |
86±10% |
76±10% |
88±10% |
76±10% |
W |
|
Trace width/spacing/width (nominal) |
4.0/4.0/4.0 |
6.0/6.0/6.0 |
3.5/3.25/3.5 |
6.0/6.0/6.0 |
mil |
|
Trace length |
0.0~0.55 |
1.0~4.0 |
0.0~0.3 |
0.0~0.5 |
inch |
|
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
20 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
30 |
mil |
|
Maximum PCB via count |
3 |
mil |
|||
|
Notes: 1.See item 2 in General Memory Routing Guidelines. |
|||||