With high-speed signaling in LPDDR3 SDRAMs, point-to-point topology is used for address and command signals to achieve the best signal integrity. However, due to pin limits on the FPGA side, control signals are routed from the FPGA to two SDRAMs in fly-by topology in a x64 two-SDRAM system. This Figure shows the control fly-by termination for LPDDR3 SDRAM.
Table: LPDDR3 SDRAM Impedance, Length, and Spacing Guidelines for Control Signals (CKE/CS/ODT) shows the LPDDR3 SDRAM impedance, length, and spacing guidelines for control signals for a x64 two-SDRAM system.
|
Parameter |
L0 |
L1 |
L2 |
L3 |
L4 |
Units |
|---|---|---|---|---|---|---|
|
Trace type |
Stripline |
Stripline |
Stripline |
Stripline |
Stripline |
- |
|
Single-ended impedance Z0 |
52±10% |
39±10% |
52±10% |
52±10% |
50±10% |
W |
|
Trace width (nominal) |
3.5 |
6.0 |
3.5 |
3.5 |
4.0 |
mil |
|
Trace length |
0.0~0.55 |
1.2~4.0 |
0.0~0.3 |
2.0~2.4 |
0.0~0.5 |
inch |
|
Spacing in cmd/addr/ctrl signals (minimum) |
4.0 |
8.0 |
4.0 |
4.0 |
8 |
mil |
|
Spacing to clock signals (minimum) |
8.0 |
20 |
8.0 |
20 |
20 |
mil |
|
Spacing to other group signals (minimum) |
8.0 |
30 |
8.0 |
30 |
30 |
mil |
|
Maximum PCB via count |
4 |
mil |
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|
Notes: 1.See item 2 in General Memory Routing Guidelines. 2.The entire trace length between two SDRAM control signal balls including breakout region should be between 2.0 to 2.4 inches. 3.Clock, address, and command point-to-point traces at the second SDRAM need to have an extra 0.5 inch added when compared to the control trace to compensate for control double loading. |
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