LPDDR3 SDRAM Interface Signal Description

UltraScale Architecture PCB Design User Guide (UG583)

Document ID

UG583

Release Date

2023-11-14

Revision

1.27 English

The LPDDR3 SDRAM interface consists of clock, control, address, command, and data signals as shown in Table: LPDDR3 SDRAM Interface Signal Description.

Table 2-61: LPDDR3 SDRAM Interface Signal Description
Signal Name	Description
CK_t, CK_c	Differential clock
Control Signals
CKE[1:0]	Clock enable
CS[1:0]_n	Chip select
ODT	DQ ODT control
Command/Address Signals
CA[9:0]	Command/address bus
Data Signals
DQ[32:0]	Data bus
DQS[3:0]_t/c	Differential data strobe
DM[3:0]	Input data mask
Notes: 1.Actual signal list might vary based on configuration.