There are two constraints requirements for each signal group in the LPDDR3 memory interface:
•Maximum length constraints
•Skew constraints
The maximum length constraints are shown in Table: LPDDR3 x32 SDRAM Maximum Length Constraints and Table: LPDDR3 x64 SDRAM Maximum Length Constraints. The maximum length is counted from the FPGA, through the PCB board, to the SDRAM package.
|
Signal Group |
Reference Figure |
Maximum Length Constraints (inches) |
|---|---|---|
|
Address/command/control |
5.83 |
|
|
Data signals |
5.83 |
|
|
Clock |
5.83 |
|
Signal Group |
Reference Figure |
Maximum Length Constraints (inches) |
|---|---|---|
|
Address/command/control |
9.00 |
|
|
Data signals |
5.83 |
|
|
Clock |
9.00 |
The skew constraints are shown in Table: LPDDR3 SDRAM Memory Skew Constraints.
|
Signal Group |
Signal Segment |
Skew Constraints (ps) |
Skew Constraints (mil) |
|---|---|---|---|
|
Address/command/control to clock(1) |
FPGA to memory device |
±4 |
±23 |
|
Data to DQS |
FPGA to memory device |
±5 |
±29 |
|
DQS_p and DQS_n |
FPGA to memory device |
2 |
12 |
|
Clock to strobe |
FPGA to memory device |
–149 to 1,796 |
–879 to 10,600 |
|
Notes: 1.This does not take into account the extra 0.5 in trace on the clock, address, and command signals in a x64 system. 2.Constraints are referred to signals within the same SDRAM. 3.For skew specifications, refer to items 3–8 in General Memory Routing Guidelines. |
|||
IMPORTANT: Package routing length must be included in both maximum length constraints and skew constraints. When minimum and maximum values are available for the package delay, use the midrange between the minimum and maximum values.
Due to the extra loading at the second DRAM in the control bus, additional trace length is needed in address, command, and clock traces at the second SDRAM in a x64 two-SDRAM system shown in This Figure.
The matching constraints for control, address, command, and clock signals are shown here:
•L1 = L3
•L2 = L3 + L4 + 0.5 in