LPDDR4 Address Copy

UltraScale Architecture PCB Design User Guide (UG583)

Document ID
UG583
Release Date
2023-11-14
Revision
1.27 English

The PS DDR interface includes a feature called address copy to reduce loading on the address/command bus when operating in LPDDR4 mode. A[5:0] are replicated on A[15:10] to allow fewer loads on the CA bus (Table: LPDDR4 Address Copy).

Table 2-49:      LPDDR4 Address Copy

MPSoC Pin

DRAM Pin

MPSoC Pin Copy

DRAM Pin

PS_DDR_A0

CA0_A

PS_DDR_A10

CA0_B

PS_DDR_A1

CA1_A

PS_DDR_A11

CA1_B

PS_DDR_A2

CA2_A

PS_DDR_A12

CA2_B

PS_DDR_A3

CA3_A

PS_DDR_A13

CA3_B

PS_DDR_A4

CA4_A

PS_DDR_A14

CA4_B

PS_DDR_A5

CA5_A

PS_DDR_A15

CA5_B